1. Field of the Invention
The present invention relates generally to the cell array architecture of nonvolatile memory devices, and more particularly to the cell array architecture of nonvolatile NAND-based NOR flash memory devices.
2. Description of Related Art
Nonvolatile memory is well known in the art. The different types of nonvolatile memory include read-only-memory (ROM), electrically programmable read only Memory (EPROM), electrically erasable programmable read only memory (EEPROM), NOR flash memory, and NAND flash memory. In current applications such as personal digital assistants, cellular telephones, notebook and laptop computers, voice recorders, global positioning systems, etc., the flash memory has become one of the more popular types of nonvolatile memory. Flash memory has the combined advantages of high density, small silicon area, low cost and can be repeatedly programmed and erased with a single low-voltage power supply voltage source.
The flash memory structures known in the art employ a charge storage mechanism and a charge trapping mechanism. In the charge storage regime, as with a floating gate nonvolatile memory, the charge representing digital data is stored on a floating gate of the device. The stored charge modifies the threshold voltage of the floating gate memory cell to determine the digital data stored. In a charge trapping regime, as in a silicon-oxide-nitride-oxide-silicon (SONOS) or metal-oxide-nitride-oxide-silicon (MONOS) type cell, the charge is trapped in a charge trapping layer between two insulating layers. The material such as silicon nitride (SiNX) in the charge trapping layer in the SONOS/MONOS devices has a relatively high dielectric constant (k).
Both N-channel and P-channel flash memory cells could be employed to form the memory array. Hereafter, the N-channel flash memory cell is used as an example for description. In general, the unit size of a NAND flash memory cell is relatively smaller than the one of a NOR flash memory cell. In the conventional one transistor (1T) NOR flash memory, it uses channel hot electron (CHE) program scheme and Fowler-Nordheim tunneling erase scheme. Due to the requirement of high enough lateral electric field and electron-hole pairs generated at N+/P+ junction with the biased voltage, the channel length can not be formed by the smallest feature size in the most advanced process because of the punch-through concern. In other words, the scalability becomes worse when the advanced technology has a small geometry such as 130 nm or below.
As for the conventional NAND flash memory N-Transistor string, it can take advantage of the smallest feature size in the most advanced process. However, the requirement of two source line (SL) and bit line (BL) select gate transistors along the NAND string to isolate from other NAND string requires certain extra percentage of overhead in the size of the whole memory array. Due to the punch-through concern on those two SL and BL select gate transistors, their channel length can not be made with the smallest feature size in the most advanced process either. In other words, the smallest feature size can only be applied to the memory cell with the cost of more percentage of overhead for the SL and BL select gate transistors.
In the NOR flash memory, there is another type called 2T NOR flash memory that is formed by one access transistor and one memory cell. No over-erase issue and less hot carrier injection (HCI) are the advantages of the 2T NOR flash memory because of the access transistor. However, the problem of punch-through effect is just moved from the memory cell to the access transistor.
U.S. Pat. No. 6,212,102 discloses a 2T NOR flash cell in which a high voltage is required across the drain and source nodes of the flash cell during FN-edge programming and a longer channel length is also required to prevent the punch-through effect. This causes a physical limitation on how small the cell can be made and in turn limits the use of the cell in ultra high integrated levels of the flash memory below 0.18 μm technology. Furthermore, the negative FN-edge programming causes device oxide degradation because the electron-hole pairs at the biased drain/TPW (triple P-Well) junction are accelerated by the voltage difference between the drain and source nodes. The more holes are trapped in the tunneling oxide, the less P/E endurance cycles will be attained.
U.S. Pat. Nos. 6,307,781 and 6,628,544 disclose improvements over U.S. Pat. No. 6,212,102 with uniform channel erase and channel program operations. However, by connecting the common source together in the array, the gate of the access device has to be applied with the most negative voltage, e.g., −3V, to turn off the path to different bit lines through the common source line. Due to this biased condition during the program operation, the program inhibit voltage, i.e., 3V-4V is supposedly isolated by the access device. However, the drain induced leakage current may occur if the channel length is scaled down. Therefore, the flash cell still faces the scaling issue and can only be manufactured with a large memory cell size.
U.S. Pat. No. 6,980,472 presents another flash memory in which both source side injection programming and FN channel programming schemes are disclosed. In the memory array, the same scaling issue exists. For the channel programming, it is similar to the one disclosed in U.S. Pat. Nos. 6,307,781 and 6,628,544. The short channel length in the access device cannot stop the drain induced leakage current to the common source line while the program inhibit voltage is applied across the drain region and the source region. In a same manner, for the source side injection programming scheme, the access device needs a longer channel length to prevent the punch-through effect. In addition, compared to the FN channel programming, the flash memory needs more program current because of the hot-electron generation.
FIG. 1 is a schematic diagram of a 2T string NAND-based NOR flash memory array 10 with separate bit lines and source lines to overcome the above mentioned drawbacks. In the array, the source lines SL0-SL1 are structured as parallel to the bit lines BL0-BL1 and orthogonal to the word lines WL0-WL3. With this structure, the program voltage and program inhibit voltage can be applied to each bit line or source line respectively while performing a program operation. Unlike the traditional array with a common source line, there is no voltage difference between the drain node and the source node of a flash cell in the memory array of FIG. 1 during the program operation. As a result, no punch through problem needs to be taken into consideration and memory size scalability can be attained. In the advanced process such as 90 nm and beyond, the advantage of the small memory cell size in the 2T string NAND-based NOR flash memory is evident.
FIG. 2A is a layout diagram 20 of the 2T string NAND-based NOR flash array shown in FIG. 1. In the layout, both the source lines SL0-SL1 and the bit lines BL0-BL1 are formed on the same metal layer. By using M1 metal layer as the bit lines and source lines, the effective memory cell size is larger because of the M1 metal layer spacing. The memory cell size can be reduced by using more metal layers to implement the bit lines and source lines.
FIG. 2B is another layout diagram 25 of the 2T string NAND-based NOR flash array shown in FIG. 1. In the layout, the source lines SL0-SL1 and the bit lines BL0-BL1 are formed by three different metal layers. By using the connection of M1 metal layer, M2 metal layer and M3 metal layer to place the bit lines and the source lines, the effective memory cell size is reduced because of the utilization of multiple metal layers to save the area.
The needs of an improved array architecture for NOR flash memories to be manufactured with the smallest feature size for cell size reduction in the advanced technology without concerns of the drain induced leakage current and punch-through issue are obvious from the above discussion.